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high voltage latch - up proof, triple/quad spdt switches data sheet adg5233/adg5234 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks a nd registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 C 2012 analog devices, inc. all rights reserved. features latch - up proof 4.5 pf off source capacitance 10 pf off drain capacitance ? 0 .6 pc c harge injection low on resistance: 16 0 ? typ ical 9 v to 22 v dual - supply operation 9 v to 4 0 v single - supply operation 48 v supply maximum ratings fully specified at 15 v, 20 v, +12 v, and +36 v v dd to v ss analog signal range human body mo del ( hbm ) esd rating 4 kv i/o port to su pplies 1 kv i/o p ort to i/o p ort 4 kv a ll other pins applications automatic test equipment data acquisition instrumentation avionics au dio and video switching communication systems functional block dia grams s1a d1 s1b s3b d3 s3a s2b d2 s2a adg5233 in1 in2 in3 en logic switches shown for a 1 input logic. 09919-001 figure 1. adg5233 tssop and lfcsp_ w q adg5234 switches shown for a 1 input logic. s1a d1 in1 s1b s2b d2 in2 s2a s4a d4 in4 s4b s3b d3 in3 s3a 09919-002 figure 2. adg5234 tssop general description the adg5233 and adg5234 are monolithic indust rial cmos analog switches comprising three independently selectable s ingle - pole, double throw (spdt) switches and four indepen - dently selectable spdt switches, respectively. all channels exhibit break - before - make switching action that prevents momentary shorting when switching channels. an en input on the adg5233 (lfcsp and tssop package s) is used to enable or disable the device. when disabled, all channels are switched off. the ultralow capacitance and charge injection of these switches make them ideal soluti ons for data acquisition and sample - and - hold ap plications, where low glitch and fast settling are required. fast switching speed coupled with high signal bandwidth make these devices suitable for video signal switching. product highlights 1. trenc h isolation guards against latch - up . a dielectric trench separates the p and n channel transistors thereby preventing latch - up even under severe overvoltage conditions. 2. ultralow c apacitance and ? 0.6 p c c harge i njection. 3. dual - supply op eration. for applications where the analog signal is bipolar, the adg5233 / adg5234 can be operated from dual supplies up to 22 v. 4. single - supply operation. for applications where the analog sig nal is unipolar, the adg5233 / adg5234 can be operated from a single - rail power supply up to 4 0 v. 5. 3 v l ogic - compatible digital in puts . v i n h = 2.0 v, v i n l = 0.8 v. 6. no v l logic power supply requ ired.
adg5233/adg5234 data sheet rev. a | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagrams ............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 15 v dual supply ....................................................................... 3 20 v dual supply ....................................................................... 4 12 v single supply ........................................................................ 5 36 v single supply ........................................................................ 6 continuous current per channel, sx or dx ..............................8 absolute maximum ratings ............................................................9 esd caution ...................................................................................9 pin configurations and function descriptions ......................... 10 typical performance characteristics ........................................... 12 te st c irc ui ts ..................................................................................... 16 terminology .................................................................................... 18 trench isolation .............................................................................. 19 applications informatio n .............................................................. 20 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 22 revision history 3/12 rev. 0 to rev. a added 16 - lead lfcsp ....................................................... universal changes to ordering guide ........................................................... 22 7 /11 revision 0: initial version
data sheet adg5233/adg5234 rev. a | page 3 of 24 specifications 15 v dual supply v dd = + 15 v 10%, v ss = ?15 v 10%, gnd = 0 v, unless otherwise noted. table 1 . parameter 25 c ?40 c to +85 c ?4 0 c to +125 c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance, r on 160 ? typ v s = 10 v, i s = ?1 ma; see figure 26 200 250 280 ? max v dd = +13.5 v, v ss = ?13.5 v on - resistance match between channels, ? r on 3.5 ? typ v s = 10 v, i s = ?1 ma 8 9 10 ? max on - resistance flatness, r flat (on) 38 ? typ v s = 10 v, i s = ?1 ma 50 65 70 ? max leakage currents v dd = +16.5 v, v ss = ?16.5 v source off leakage, i s (off ) 0.0 2 na typ v s = 10 v, v d = ? 10 v; see figure 28 0.1 0.2 0.4 na max drain off leakage, i d (off ) 0.0 2 na typ v s = 10 v, v d = ? 10 v; see figure 28 0.1 0. 2 0 .4 na max channel on leakage, i d (on), i s (on) 0.0 8 na typ v s = v d = 10 v; see figure 25 0.2 0. 3 0 . 9 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 trans ition time, t transition 170 ns typ r l = 300 ?, c l = 35 pf 210 250 280 ns max v s = 10 v; see figure 31 t on ( en ) 175 ns typ r l = 300 ?, c l = 35 pf 215 255 290 ns max v s = 10 v; see fig ure 33 t off ( en ) 80 ns typ r l = 300 ?, c l = 35 pf 100 115 125 ns max v s = 10 v; see figure 33 break - before - make time delay, t d 60 ns typ r l = 300 ?, c l = 35 pf 30 ns min v s1 = v s2 = 10 v; see figure 32 charge injection, q inj ? 0 .6 pc typ v s = 0 v, r s = 0 ?, c l = 1 nf; see figure 34 off isolation ? 75 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz ; see figure 29 channel - to - channel crosstalk ? 80 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; figure 27 ?3 db bandwidth 205 mhz typ r l = 50 ?, c l = 5 pf; see figure 30 insertion loss ? 6.3 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 30 c s (off ) 4.5 pf typ v s = 0 v, f = 1 mhz c d (off ) 10 pf typ v s = 0 v, f = 1 mhz c d (on), c s (on) 15 pf typ v s = 0 v, f = 1 mhz
adg5233/adg5234 data sheet rev. a | page 4 of 24 parameter 25 c ?40 c to +85 c ?4 0 c to +125 c unit test conditions/comments power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 45 a typ digital inputs = 0 v or v dd 55 70 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 9/22 v mi n/v max gnd = 0 v 1 guaranteed by design; not subject to production test. 20 v dual supply v dd = + 20 v 10%, v ss = ?20 v 10%, gnd = 0 v, unless otherwise noted. table 2 . parameter 25 c ?40 c to +85 c ?40 c to +125 c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance, r on 140 ? typ v s = 15 v, i s = ?1 ma; see figure 26 160 200 230 ? max v dd = +18 v, v ss = ?18 v on - resistance match between channels, ? r on 3.5 ? typ v s = 15 v, i s = ?1 ma 8 9 10 ? max on - resistance flatness, r flat (on) 33 ? typ v s = 15 v, i s = ?1 ma 45 55 60 ? max leakage currents v dd = +22 v, v ss = ?22 v source off leakage, i s (off ) 0.02 na typ v s = 15 v, v d = ? 15 v; see figure 28 0.1 0.2 0.4 na max drain off leakage, i d (off ) 0.02 na typ v s = 15 v, v d = ? 15 v; see figure 28 0.1 0.2 0.4 na max channel on leakage, i d (on), i s (on) 0.08 na typ v s = v d = 15 v; see figure 25 0.2 0.3 0.9 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 transition time, t transition 170 ns typ r l = 300 ?, c l = 35 pf 200 235 260 ns max v s = 10 v; see figure 31 t on ( en ) 165 ns typ r l = 300 ?, c l = 35 pf 200 240 265 ns max v s = 10 v; see figure 33 t off ( en ) 80 ns typ r l = 300 ?, c l = 35 pf 95 105 115 ns max v s = 10 v; see figure 33 break - before - make time delay, t d 50 ns typ r l = 300 ?, c l = 35 pf 30 ns min v s1 = v s2 = 10 v; see figure 32 charge injection, q inj 0 pc typ v s = 0 v, r s = 0 ?, c l = 1 nf; see figure 34 off isolation ? 75 db typ r l = 50 ?, c l = 5 pf, f = 1mhz; see fi gure 29 channel - to - channel crosstalk ? 80 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; see figure 27 ?3 db bandwidth 210 mhz typ r l = 50 ?, c l = 5 pf; see figure 30 insertion loss ? 5.5 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 30
data sheet adg5233/adg5234 rev. a | page 5 of 24 parameter 25 c ?40 c to +85 c ?40 c to +125 c unit test conditions/comments c s (off ) 4.5 pf typ v s = 0 v, f = 1 mhz c d (off ) 10 pf typ v s = 0 v, f = 1 mhz c d (on), c s (on) 15 pf typ v s = 0 v, f = 1 mhz power requirements v dd = +22 v, v ss = ?22 v i dd 50 a typ digital inputs = 0 v or v dd 70 110 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 9/22 v min/v max gnd = 0 v 1 guaranteed by desi gn; not subject to production test. 12 v single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 3 . parameter 25 c ?40 c to +85 c ?40 c to +125 c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance, r on 360 ? typ v s = 0 v to 10 v, i s = ?1 ma; see figure 26 500 610 700 ? max v dd = 10.8 v, v ss = 0 v on - resistance match between channels, ? r on 5.5 ? typ v s = 0 v to 10 v, i s = ?1 ma 20 21 22 ? max on - resistance flat ness, r flat (on) 170 ? typ v s = 0 v to 10 v, i s = ?1 ma 280 335 370 ? max leakage currents v dd = 13.2 v, v ss = 0 v source off leakage, i s (off ) 0.02 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 28 0.1 0.2 0.4 na max drain off leakage, i d (off ) 0.02 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 28 0.1 0.2 0.4 na max channel on leakage, i d (on), i s (on) 0.08 na typ v s = v d = 1 v/10 v; see figure 25 0.2 0.3 0.9 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 transition time, t transition 235 ns typ r l = 300 ?, c l = 35 pf 295 365 410 ns max v s = 8 v ; see figure 31 t on ( en ) 240 ns typ r l = 300 ? , c l = 35 pf 305 380 430 ns max v s = 8 v; see figure 33 t off ( en ) 70 ns typ r l = 300 ? , c l = 35 pf 90 105 115 ns max v s = 8 v; see figure 33 break - before - make time delay, t d 125 ns typ r l = 300 ? , c l = 35 pf 65 ns min v s1 = v s2 = 8 v; see figure 32 charge injection, q inj 0 pc typ v s = 6 v, r s = 0 ? , c l = 1 nf; see figure 34
adg5233/adg5234 data sheet rev. a | page 6 of 24 parameter 25 c ?40 c to +85 c ?40 c to +125 c unit test conditions/comments off isolation ? 75 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 29 channel - to - channel crosstalk ? 80 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; see figure 27 ?3 db bandwidth 172 mhz typ r l = 50 ? , c l = 5 pf; see figure 30 insertion loss ? 8.7 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 30 c s (off ) 5 pf typ v s = 6 v, f = 1 mhz c d (off ) 11 pf typ v s = 6 v, f = 1 mhz c d (on), c s (on) 16 pf typ v s = 6 v, f = 1 mhz power requirements v dd = 13.2 v i dd 40 a typ digital inputs = 0 v or v dd 50 65 a max v dd 9/40 v min/v max gnd = 0 v, v ss = 0 v 1 guaranteed by design; not subject to production test. 36 v single supply v dd = 36 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 4 . parameter 25 c ?40 c to +85 c ?40 c to +125 c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance, r on 140 ? typ v s = 0 v to 30 v, i s = ?1 ma; see figure 26 170 215 245 ? m ax v dd = 32.4 v, v ss = 0 v on - resistance match between channels, ? r on 3.5 ? typ v s = 0 v to 30 v, i s = ?1 ma 8 9 10 ? max on - resistance flatness, r flat (on) 35 ? typ v s = 0 v to 30 v, i s = ?1 ma 50 60 65 ? max leakage currents v dd = 39.6 v, v ss = 0 v source off leakage, i s (off ) 0.02 na typ v s = 1 v/30 v, v d = 30 v/1 v; see figure 28 0.1 0.2 0.4 na max drain off leakage, i d (off ) 0.02 na typ v s = 1 v/30 v, v d = 30 v/1 v; se e figure 28 0.1 0.2 0.4 na max channel on leakage, i d (on), i s (on) 0.08 na typ v s = v d = 1 v/30 v; see figure 25 0.2 0.3 0.9 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 transition time, t transition 205 ns typ r l = 300 ?, c l = 35 pf 255 275 290 ns max v s = 18 v ; see figure 31 t on ( en ) 200 ns typ r l = 300 ? , c l = 35 pf 240 265 290 ns max v s = 18 v; see fi gure 33 t off ( en ) 85 ns typ r l = 300 ? , c l = 35 pf 115 115 115 ns max v s = 18 v; see figure 33
data sheet adg5233/adg5234 rev. a | page 7 of 24 parameter 25 c ?40 c to +85 c ?40 c to +125 c unit test conditions/comments break - before - make time delay, t d 65 ns typ r l = 300 ? , c l = 35 pf 35 ns min v s1 = v s2 = 18 v; see figure 32 charge injection, q inj ? 0 .6 pc typ v s = 18 v, r s = 0 ? , c l = 1 nf; see figure 34 off isolation ? 75 db typ r l = 50 ?, c l = 5 pf, f = 1 m hz; see figure 29 channel - to - channel crosstalk ? 80 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; see figure 27 ?3 db bandwidth 190 mhz typ r l = 50 ? , c l = 5 pf; see figure 30 insertion loss ? 5.9 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 30 c s (off ) 4.5 pf typ v s = 18 v, f = 1 mhz c d (off ) 10 pf typ v s = 18 v, f = 1 mhz c d (on), c s (on) 15 pf typ v s = 18 v, f = 1 mhz power requirements v dd = 39.6 v i dd 80 a typ digital inputs = 0 v or v dd 100 130 a max v dd 9/40 v min/v max gnd = 0 v, v ss = 0 v 1 guaranteed by design; not subject to production test.
adg5233/adg5234 data sheet rev. a | page 8 of 24 continuous current p er channel, s x or d x tab le 5 . adg5233 parameter 25 c 85 c 125 c unit continuous current, s x or d x v dd = +15 v, v ss = ?15 v tssop ( ja = 112.6c/w) 24 16 11 ma maximum lfcsp ( ja = 30.4c/w) 42 26.5 15 ma maximum v dd = +20 v, v ss = ?20 v tssop ( ja = 112.6c/w) 26 17 11 ma maximum lfcsp ( ja = 30.4c/w) 46 28 15 ma maximum v dd = 12 v, v ss = 0 v tssop ( ja = 112.6c/w) 17 12 7.7 ma maximum lfcsp ( ja = 30.4c/w) 24 17 11 ma maximum v dd = 36 v, v ss = 0 v tssop ( ja = 112.6c/w) 25 17 11 ma maximum lfcsp ( ja = 30.4c/w) 45 28 15 ma maximum table 6 . adg5234 parameter 25 c 85 c 125 c unit continuous current, s x or d x v dd = +15 v, v ss = ?15 v tssop ( ja = 112.6c/w) 21 15 10 ma maximum v dd = +20 v, v ss = ?20 v tssop ( ja = 112.6c/w) 22 15 10 ma maximum v dd = 12 v, v ss = 0 v tssop ( ja = 112.6c/w) 15 11 7 ma maximum v dd = 36 v, v ss = 0 v tssop ( ja = 112.6c/w) 22 15 10 ma maximum
data sheet adg5233/adg5234 rev. a | page 9 of 24 absolute maximum rat ings t a = 25 c, unless otherwise noted. table 7 . parameter ratin g v dd to v ss 48 v v dd to gnd ?0.3 v to +48 v v ss to gnd +0.3 v to ?48 v analog inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first digital inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, sx or dx pi ns adg5233 76 ma (pulsed at 1 ms, 10% duty cycle maximum) adg5234 67 ma (pulsed at 1 ms, 10% duty cycle maximum) continuous current, sx or d x 2 data + 15% te mperature range operating ? 40c to +125c storage ? 65c to +150c junction temperature 150c thermal impedance, ja 16- lead tssop (4 - layer board) 112.6c/w 20- lead tssop (4 - layer board) 143c/w 16- lead lfcsp (4 - layer board) 30.4 c/w reflow soldering peak temperature, pb fr ee 260(+0/ ? 5)c human body model (hbm) esd i/o port to supplies 4 kv i/o port to i/o port 1 kv all other p ins 4 kv 1 overvoltages at the inx, sx, and dx pins are clamped by internal diodes. limit current to the maximum ratings given. 2 see table 5 and table 6 . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of th e device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum ra ting can be applied at any one time. esd caution
adg5233/adg5234 data sheet rev. a | page 10 of 24 pin configurations a nd function descript ions v dd 1 s1a 2 d1 3 s1b 4 gnd 16 in1 15 en 14 v ss 13 s2b 5 s3b 12 d2 6 d3 11 s2a 7 s3a 10 in2 8 in3 9 adg5233 top view (not to scale) 09919-003 figure 3. adg5233 tssop pin configuration notes 1. exposed pad tied to substrate, v ss . 1 d1 2 s1b 3 s2b 4 d2 11 v ss 12 en 10 s3b 9 d3 5 s2a 6 in2 7 in3 8 s3a 15 v dd 16 s1a 14 gnd 13 in1 top view (not to scale) adg5233 09919-004 figure 4. adg5233 lfcsp_ w q pin configuration table 8 . adg5233 pin function descriptions pin n o. neonic description tssop lfcsp 1 15 v dd most positive power supply potential. 2 16 s1a source terminal 1a. this pin c an be an input or an output. 3 1 d1 drain terminal 1. this pin c an be an input or an output. 4 2 s1b source terminal 1b. this pin c an be an input or an output. 5 3 s2b source terminal 2b. this pin c an be an input or an output. 6 4 d2 drain terminal 2. this pin c an be an input or an output. 7 5 s2a source terminal 2a. this pin c an be an input or an output. 8 6 in2 logic control input 2 . 9 7 in3 logic control input 3 . 10 8 s3a source terminal 3a. this pin c an be an input or an output. 11 9 d3 drain terminal 3. this pin c an be an input or an output. 12 10 s3b source terminal 3b. this pin c a n be an input or an output. 13 11 v ss most negative po wer supply potential. in single - supply applicatio ns, this pin c an be connected to ground. 14 12 en active low digital input. when high, the device is disa bled and all switches are off. when low, inx logic inputs determine the on switches. 15 13 in1 logic contr ol input 1 . 16 14 gnd ground (0 v) reference. ep exposed pad the exposed pad is connected internally. for increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, v ss . tabl e 9 . adg5233 truth table en in sa s b 1 x 1 off off 0 0 off on 0 1 on off 1 x is dont care.
data sheet adg5233/adg5234 rev. a | page 11 of 24 in1 1 s1a 2 d1 3 s1b 4 in4 20 s4a 19 d4 18 s4b 17 v ss 5 v dd 16 gnd 6 nc 15 s2b 7 s3b 14 d2 8 d3 13 s2a 9 s3a 12 in2 10 in3 11 adg5234 top view (not to scale) nc = no connect. do not connect to this pin. 09919-005 figure 5. adg5234 tssop pin configuration table 10. adg5234 pin function descriptions pin no. mnemonic description 1 in1 logic control input 1. 2 s1a source terminal 1a. this pin can be an input or an output. 3 d1 drain terminal 1. this pin can be an input or an output. 4 s1b source terminal 1b. this pin can be an input or an output. 5 v ss most negative power supply potential. in single - supply app lications, this pin can be connected to ground. 6 gnd ground (0 v) reference. 7 s2b source terminal 2b. this pin can be an input or an output. 8 d2 drain terminal 2. this pin can be an input or an output. 9 s2a source terminal 2a. this pin can be an in put or an output. 10 in2 logic control input 2. 11 in3 logic control input 3. 12 s3a source terminal 3a. this pin can be an input or an output. 13 d3 drain terminal 3. this pin can be an input or an output. 14 s3b source terminal 3b. this pin can be a n input or an output. 15 nc no connect. th is pin is open. 16 v dd most positive power supply potential. 17 s4b source terminal 4b. this pin can be an input or an output. 18 d4 drain terminal 4. this pin can be an input or an output. 19 s4a source termi nal 4a. this pin can be an input or an output. 20 in4 logic control input 4. table 11. adg5234 truth table inx sxa sxb 0 off on 1 on off
adg5233/adg5234 data sheet rev. a | page 12 of 24 typical performance characteristics 160 0 20 40 60 80 100 120 140 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 on resistance (?) v s , v d (v) t a = 25c v dd = +18v v ss = ?18v v dd = +20v v ss = ?20v v dd = +22v v ss = ?22v 09919-006 figure 6 . on resistance as a function of v s , v d ( 20 v dual supply ) 250 200 150 100 50 0 ?20 ?15 ?10 ?5 0 5 10 15 20 on resistance (?) v s , v d (v) t a = 25c v dd = +9v v ss = ?9v v dd = +13.2v v ss = ?13.2v v dd = +15v v ss = ?15v v dd = +16.5v v ss = ?16.5v 09919-007 figure 7. on resistance as a function of v s , v d ( 15 v dual supply) 500 450 400 350 300 250 200 150 100 50 0 0 14 12 10 8 6 4 2 on resistance (?) v s , v d (v) t a = 25c v dd = 9v v ss = 0v v dd = 10.8v v ss = 0v v dd = 12v v ss = 0v v dd = 13.2v v ss = 0v 09919-008 figure 8. on resistance as a funct ion of v s , v d ( 12 v single supply) 160 140 120 100 80 60 40 20 0 0 40 35 30 25 20 15 10 5 on resistance (?) v s , v d (v) t a = 25c v dd = 32.4v v ss = 0v v dd = 36v v ss = 0v v dd = 39.6v v ss = 0v 09919-009 figure 9. on resistance as a function of v s , v d ( 36 v single supply) 250 200 150 100 50 0 ?15 ?10 ?5 0 5 10 15 on resistance (?) v s, v d (v) v dd = +15v v ss = ?15v t a = +125c t a = +85c t a = +25c t a = ?40c 09919-010 figure 10 . on resistance as a function of v s (v d ) for different temperatures, 15 v dual supp ly 200 160 120 80 40 180 140 100 60 20 0 ?20 ?15 ?10 ?5 0 5 10 20 15 on resistance (?) v s, v d (v) v dd = +20v v ss = ?20v t a = +125c t a = +85c t a = +25c t a = ?40c 09919-0 1 1 figure 11 . on resistance as a function of v s (v d ) for different temperatures, 20 v dual supply
data sheet adg5233/adg5234 rev. a | page 13 of 24 500 400 300 200 100 450 340 250 150 50 0 0 2 4 6 8 10 12 on resistance (?) v s, v d (v) v dd = 12v v ss = 0v t a = +125c t a = +85c t a = +25c t a = ?40c 09919-012 figure 12 . on resistance as a function of v s (v d ) for different temperatures, 12 v single supply 250 200 100 150 50 0 0 35 30 25 20 15 10 5 on resistance (?) v s, v d (v) v dd = 36v v ss = 0v t a = +125c t a = +85c t a = +25c t a = ?40c 09919-013 figure 13 . on resistance as a function of v s (v d ) for different temperatures, 36 v single supply 50 ?250 ?200 ?150 ?100 ?50 0 0 25 50 75 100 125 leakage current (pa) temperature (c) v dd = +15v v ss = ?15v v bias = +10v/?10v i d , i s (on) ? ? i s (off) + ? i d (off) ? + i d (off) + ? i s (off) ? + i d , i s (on) + + 09919-014 figure 14 . leakage currents as a function of temperature, 15 v dual supply 100 ?200 ?150 ?100 ?50 0 50 0 25 50 75 100 125 leakage current (pa) temper a ture (c) v dd = +20v v ss = ?20v v bias = +15v/?15v i d , i s (on) + + i d , i s (on) ? ? i s (off) + ? i d (off) ? + i d (off) + ? i s (off) ? + 09919-015 figure 15 . leakage currents as a function of temperature, 20 v dual supply 100 ?700 ?600 ?500 ?400 ?300 ?200 ?100 0 0 25 50 75 100 125 leakage current (pa) temper a ture (c) v dd = 12v v ss = 0v v bias = 1v/10v i d , i s (on) ? ? i s (off) + ? i d (off) ? + i d (off) + ? i s (off) ? + i d , i s (on) + + 09919-016 figure 16 . leakage currents as a function of temperature, 12 v single supply 200 ?1000 ?800 ?600 ?400 ?200 0 0 25 50 75 100 125 leakage current (pa) temperature (c) v dd = 36v v ss = 0v v bias = 1v/30v i d , i s (on) ? ? i s (off) + ? i d (off) ? + i d (off) + ? i s (off) ? + i d , i s (on) + + 09919-017 figure 17 . leakage currents as a function of temperature, 36 v single supply
adg5233/adg5234 data sheet rev. a | page 14 of 24 0 ?120 ?100 ?80 ?60 ?40 ?20 10k 100k 1g 100m 10m 1m off isolation (db) frequency (hz) t a = 25c v dd = +15v v ss = ?15v 09919-018 figure 18 . off isolation vs. frequency , 15 v dual supply 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 10k 100k 1g 100m 10m 1m crosstalk (db) frequency (hz) t a = 25c v dd = +15v v ss = ?15v between sxa and sxb between s1x and s2x 09919-019 figure 19 . crosstalk vs. frequency , 15 v dual supply 14 12 8 4 10 6 2 ?4 ?2 0 ?20 ?10 0 10 20 30 40 charge injection (pc) v s (v) t a = 25c source to drain v dd = +20v v ss = ?20v v dd = +15v v ss = ?15v v dd = +36v v ss = 0v v dd = +12v v ss = 0v 09919-020 figure 20 . charge injection vs. source voltage , source to drain 0 ?120 ?100 ?80 ?60 ?40 ?20 1k 10k 100k 10m 1m acpssr (db) frequency (hz) t a = 25c v dd = +15v v ss = ?15v no decoupling capacitors decoupling capacitors 09919-021 figure 21 . acpsrr vs. frequency , 15 v dual supply
data sheet adg5233/adg5234 rev. a | page 15 of 24 0 ?12 ?10 ?8 ?6 ?4 ?2 100k 1g 100m 10m 1m attenuation (db) frequency (hz) t a = 25c v dd = +15v v ss = ?15v 09919-023 figure 22 . bandwidth 300 0 50 100 150 200 250 ?40 ?20 120 100 80 60 40 20 0 time (ns) temperature (c) v dd = +12v, v ss = 0v v dd = +36v, v ss = 0v v dd = +15v, v ss = ?15v v dd = +20v, v ss = ?20v 09919-024 figure 23 . t transition times vs. temperature ?15 ?10 ?5 0 5 10 15 v s (v) 0 20 15 10 5 capacitance (pf) t a = 25c v dd = +15v v ss = ?15v source/drain on drain off source off 09919-025 figure 24 . capacitance vs. source voltage, 15 v dual supply
adg5233/adg5234 data sheet rev. a | page 16 of 24 test circuits v d sx dx a i d (on) nc nc = no connect 09919-027 figure 25 . on leakage sx dx v s v i ds 09919-028 figure 26 . on resistance channel-to-channel crosstalk = 20 log v out gnd sxa dx sxb v out network analyzer r l 50 r 50 v s v s v dd v ss 0.1f v dd 0.1f v ss inx 09919-029 figure 27 . channel - to - channel crosstalk sx dx v s a a v d i s (off) i d (off) 09919-031 figure 28 . off leakage v out 50 network analyzer r l 50 in v in sxb sxa dx v s off isolation = 20 log v out v s v dd v ss 0.1f v dd 0.1f v ss 50 gnd nc 09919-030 figure 29 . off isolation v out 50 network analyzer r l 50 inx v in sxb sxa dx insertion loss = 20 log v s v out with switch v out without switch v dd v ss 0.1f v dd 0.1f v ss 50 gnd nc 09919-033 figure 30 . bandwidth
data sheet adg5233/adg5234 rev. a | page 17 of 24 inx v out dx sxa v dd v ss v dd v ss gnd c l 35pf sxb v in v s 0.1f 0.1f r l 300 50% 50% 90% 50% 50% 90% t on transition t off transition v in v out v in 09919-100 figure 31 . switching timing inx dx sxa gnd sxb v s v dd v ss 0.1f v dd 0.1f v ss v out c l 35pf r l 300? v in t d t d v in v out 80% 09919-035 figure 32 . break - before - make delay, t d output inx 50? 300? gnd sxa sxb dx 35pf v in en v dd v ss v dd v ss v s 3v 0v output 50% 50% t off (en) t on (en) 0.9v out 0.1v out enable drive (v in ) 09919-101 figure 33 . enable delay, t on ( en ), t off ( en ) gnd v dd v ss 0.1f v dd 0.1f v ss v in sxa v out sxb dx nc v s inx c l 1nf on off v in (normally closed switch) v in (normally open switch) v out q inj = c l v out v out 09919-037 figure 34 . charge injection
adg5233/adg5234 data sheet rev. a | page 18 of 24 terminology i dd i dd represents the positive supply current. i ss i ss represents the negative supply current. v d , v s v d and v s represent the analog voltage on terminal d x and terminal s x , respectively. r on r on is the o hmic resistance between terminal d x and terminal s x . ? r on ? r on repre sents t he d ifference between the r on of any two channels . r flat (on) the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range is represented by r flat (on) . i s (off) i s (off) is the source lea kage current with the switch off. i d (off) i d (off) is the drain leakage current with the switch off. i d (on), i s (on) i d (on) and i s (on) represent the channel leakage currents with the switch on. v inl v inl is the maximum input voltage for logic 0. v inh v inh is the minimum input voltage for logic 1. i inl , i inh i inl and i inh represent the low and high input currents of the digital inputs. c d (off) c d (off) represents the off switch drain capacitance, which is measured with reference to ground. c s (off) c s (off) represents the off switch source capacitance, which is measured with reference to ground. c d (on), c s (on) c d (on) and c s (on) represent on switch capacitances, which are measured with reference to ground. c in c in represents digital in put capacitance. t on ( en ) t on ( en ) represents the d elay time between the 50% and 90% points of the digital input and switch on condition. t off ( en ) t off ( en ) represents the d elay tim e between the 50% and 90% points of the digital input and switch off condition. t trans ition delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. t d t d represents th e o ff time measured between the 80% point of both sw itches when switching from one address state to another. off isolation off isolation is a measure of unwanted signal coupling through an off channel. charge injection charge injection is a measure of th e glitch impulse transferred from the digital input to the analog output during switching. crosstalk crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. bandwidth bandwidth is t he frequency at which the output is attenuated by 3 db. on response on response is t he frequency response of the on switch. ac power supply rejection ratio (acpsrr) acpsrr is a measure of the ability of a part to avoid coupling noise and spurious signals that ap pear on the supply voltage pin to the output of the switch. the dc voltage on the device is modulated by a sine wave of 0.62 v p - p. the ratio of the amplitude of the signal on the output to the amplitude of the modulation is the acpsr r.
data sheet adg5233/adg5234 rev. a | page 19 of 24 trench i solation in the adg5233 / adg5234 , an insulating oxide layer (trench) is placed between the nmos and the pmos transistors of each cmos switch. parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch - up proof switch. in junction isolation, the n and p wells of the pmos and nmos transistors form a diode that is reverse - biased under no rmal operation. however, during overvoltage conditions, this diode can become forward - biased. a silicon controlled rectifier (scr) type circuit is formed by the two transistors causing a significant amplification of the current that , in turn, leads to latc h - up. with trench isolation, this diode is removed, and the result is a latch - up proof switch. nmos pmos p w e l l n w e l l buried oxide layer handle wafer t r e n c h 09919-038 figure 35 . trench isolation
adg5233/adg5234 data sheet rev. a | page 20 of 24 applications informa tion the adg5 2 xx family of switches and multiplexers provide a robust solution for instrumentation, i ndustrial, automotive , aero - space , and other harsh environments that are prone to latch - up, which is an undesirable high current state that can lead to device failure and persist s until t he power supply is turned off. the adg5233 / adg5234 high voltage switches allow single - supply operation from 9 v to 40 v and dual supply operation from 9 v to 22 v.
data sheet adg5233/adg5234 rev. a | page 21 of 24 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 36 . 16 - lead thin shrink small outline package [tssop] (ru - 16) dimensions shown in millimeters 2.70 2.60 sq 2.50 compliant t o jedec standards mo-220-wggc. 1 0.65 bsc b o t t o m v i e w t o p v i e w 1 6 5 8 9 1 2 1 3 4 e x p o s e d p a d pin 1 indica t or 4.10 4.00 sq 3.90 0.45 0.40 0.35 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.20 min coplanari ty 0.08 pin 1 indica t or 0.35 0.30 0.25 for proper connection of the exposed pad, refer to the pin configurat ion and function descriptio ns section of this data sheet. 08-16- 2010-c figure 37 . 16 - lead lead frame chip scale package [lfcsp_ w q] 4 mm 4 mm body, very very thin quad (cp - 16 - 17) dimension s shown in millimeters compliant to jedec standards mo-153-ac 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 coplanarity 0.10 figure 38 . 20 - lead thin shrink small outline package [tssop] (ru - 20) dimensions shown in millimeters
adg5233/adg5234 data sheet rev. a | page 22 of 24 ordering guide model 1 temperature range description en p in package option adg5233 bruz ?40c to +125c 16- lead thin shrink small outline package [ tssop ] yes ru -16 adg5233 bruz - rl7 ?40c to +125c 16- lead thin shrink small outline package [ tssop ] yes ru -16 adg5233bcpz - rl7 ?40c to +125c 16- lead lead f rame chip scale package [lfcsp_w q] ye s cp -16-17 adg5234 b ruz ?40 c to +125 c 20- lead thin shrink small outline package [tssop] no ru -20 adg5234 b ruz - rl7 ?40 c to +125 c 20- lead thin shrink small outline package [tssop] no ru -20 1 z = rohs compliant part.
data sheet adg5233/adg5234 rev. a | page 23 of 24 notes
adg5233/adg5234 data sheet rev. a | page 24 of 24 notes ? 2 011 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09919 - 0 - 3/12(a)

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